1. Field of the Invention
The present invention is related to integrated circuit (IC) and chip design systems and more particularly to computer aided design (CAD) systems for designing ICs and IC chips.
2. Background Description
A typical integrated circuit (IC) chip includes a stack of several sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and wires that connect the devices into circuits. Each of these layers of shapes, also known as mask levels or just “levels,” may be created or printed optically through well known photolithographic masking, photo-developing and level definition techniques, e.g., etching, implanting, deposition and etc.
Normally, a chip designer creates an electrical and/or logic representation of a new circuit that is converted to a chip/circuit layout. The chip/circuit layout is converted to mask shapes that are printed on photolithographic masks. Depending upon the particular design, each of these layers may include several hundreds of millions or even billions of mask shapes. Each photolithographic mask is used to print a pattern on a semiconductor wafer, which may define local wafer properties or one of the chip/circuit layers. Mask errors translate to chip errors that can cause chip defects. Even the resulting defective chips are functional, the design may be marginal, reducing chip yield.
Consequently, as these masks become increasingly complex, generating complex masks has become more expensive, requiring increased design creativity and effort for lithographic patterning and for manipulating the design data flow to manufacturing. Thus, manufacturing costs and risks inherent in making these complex patterns have made ineffective and obsoleted some state of the art layout methodologies and computer-aided design tools that had otherwise been used.
One approach that has proven effective in simplifying and making these complex designs more manufacturable is in representing portions of a physical design in a compact format, now known as the gridded glyph geometric objects (L3GO) format. L3GO is described in U.S. Pat. No. 7,536,664, “Physical Design System And Method” to Cohn et al. Especially where design shapes are relatively regular, e.g., logic chips with mainly rectangular contacts, diffusions, gates and wring, Cohn et al. has proven effective in reducing the design and manufacturing costs and risks. However, Cohn et al. has not yet been applied, effectively, to circuits with features that may be process dependent and require special treatment, e.g., feature-specific design ground rules and checking. Such circuits that require special treatment may include, for example, Static Random Access Memory (SRAM) cells and decoupling capacitors, body contacts, diodes, polysilicon resistors, fuses, or bonding pads, e.g., Controlled Collapse Chip Connections (C4s).
Designers use an ad-hoc approach with state of the art SRAM cell design, for example. SRAM cells are designed for compactness (density) and signal balance. Typically, such an ad-hoc approach results in choosing irregular design shapes that are not easily represented in L3GO format. Likewise fuses require unique spacing to other features and a window above each fuse. This requires one or more additional mask steps or, a variation of one or more mask steps, to open the window. Checking these special cases requires checking that is unnecessary for the rest of the design. However, state of the art design rule checkers, for example, check the entire chip with compliance with each ground rule, including these feature-specific rules.
Consequently, insuring chip-wide compliance with these complicated feature-specific rules has reduced productivity. In addition to designer effort in designing to and verifying compliance with (checking) regular ground rules, for designers using special case cells (i.e., with these special case circuits), design and compliance is even more complicated and time consuming. Not only have these feature-specific rules complicated ground rule checker coding, for example, ground rule checker results have been complicated too and are difficult designers to understand. If one cannot understand the ground rule checker results, one cannot identify and fix violations. Moreover, these complicated rules have hampered design improvements from checking feedback, e.g., to adjust a design as process learning proceeds.
Thus, there is a need for design tools and methods that represent IC components that include specialized, process dependent features in an effective, useable and understandable format for designers; that facilitate faster IC checking (e.g., ground rules) than for the same IC otherwise checked with traditional tools, such as with the IC represented in a conventional format; that may be easily integrated into current design entry and flows, especially L3GO; and that facilitates IC design improvement after the design is complete.